Math operations on ARM-M4 crash when PWM interrupt is on

Question:

When I turn off the PWM timer overflow interrupt (+-15Khz) operations occur normally. But when it is on the processor gets lost in floating point operations. I follow the debug in step mode but at some point the debug does not return and it is as if it was running just giving another pause that always falls into the described interruption.

I'm using a K20 without FPU from Freescale and I asked over there in the community but they didn't even care. I've already increased the Stack but nothing to improve. I had the same problem with an S08PA , but in this one I just had to download the timer overflow occurrence (from 20Khz to 15Khz) that worked correctly.

Edit: Not actually a firmware as I'm stuck on this issue. There is only the PWM interrupt and the routine to generate the Sine table.

// Gerador da tabela
void PWMInit(){

float a;
int i,r;

// Combine mode Pulse = CN+1 - CN
// Complementary mode : N+1 = Inv(N) 

Motor.DutyMax = FTM0_MOD - FTM0_CNTIN;
Motor.DutyZero = Motor.DutyMax >> 1;


Motor.Frequencia = 60;

Motor.MaxSamples = PWMFreq / Motor.Frequencia;
Motor.VMod = (Motor.DutyMax / 60) * Motor.Frequencia;
Motor.IncTabela = (float) 1000.0f / Motor.MaxSamples;
Motor.Div = (((long) MAXTABELA / Motor.VMod));
/*
for (i=0, a=0; i < Motor.MaxSamples; i++, a += Motor.IncTabela ) {
    r = SinT[(int)(a + 0.5f)];
    r = r / Motor.Div;
    r = Motor.DutyZero + r;
    TabelaGerada[i] =  (uint16_t) r;
}
*/
float ri = (2*PI) / Motor.MaxSamples;
float rr = 0;
for (i=0; i < Motor.MaxSamples; i++) {
    TabelaGerada[i] =  Motor.DutyZero * ((float) 1.0f + sin(rr));
    rr = rr + ri;
}

SetW(100);
SetV(500);
SetU(900);

FTM0_SYNC |= (FTM_SYNC_SWSYNC_MASK | (1 << 7)); 


}

// Interrupção
PE_ISR(EstouroDoTimerFTM0){
(void)(FTM0_SC == 0U);

Counter = 0;
}

Answer:

I caught. It happens that the Wizard Processor Expert did not disable the interrupts of the last two channels that were not used (motors only use 6 channels). So channels 6 and 7 had 'channel match' interrupts enabled and being triggered in undefined locations.